1. Field of the Invention
The present invention relates generally to a non-volatile memory device, and more particularly, to improvement of EEPROM type non-volatile semiconductor memory devices having a self-aligned structure. The invention relates to a manufacturing method therefor.
2. Description of the Background Art
FIG. 8 is a block diagram showing the structure of a conventional EEPROM.
Referring to FIG. 8, the EEPROM comprises a memory array 50 including memory cells, a row address buffer 51 for receiving a row address signal from the exterior, a column address buffer 52 for receiving a column address signal, a row decoder 53 and a column decoder 54 for decoding the address signals to supply voltage to a word line and a bit line specified by a specific memory cell, a sense amplifier 56 for reading a signal stored in the memory cell specified by the two decoders 53 and 54 through a Y gate 55, an output buffer 57 for outputting the read signal and a control signal input buffer 58 for receiving control signals from the exterior and supplying the same to the respective parts.
The sense amplifier 56 is adapted to detect and amplify the signal stored in the memory cell to supply the same to the output buffer 57.
FIG. 9 is a circuit diagram concretely showing the structure of the memory array 50 and the Y gate 55 shown in FIG. 8.
Referring to FIG. 9, the Y gate 55 includes a transistor 68 which is connected between an I/0 line 70 and a bit line 5 and another transistor 69 which is connected between a CG line 71 and a control gate line 21. A Y gate signal Y2 is supplied to the gates of the transistors 68 and 69. Transistors for receiving a Y gate signal Y1 are connected similarly to the above.
The memory array 50 is illustrated with 4-bit memory cells. For example, a memory cell includes a memory transistor 63 having a floating gate and a select transistor 62 whose gate is connected to a word line 20 for supplying a signal stored in the memory transistor 63 to the bit line 5. Another select transistor 64 is so connected that its gate is connected to the word line 20 for supplying a signal from the control gate line 21 to the gate of the memory transistor 63. The sources of the memory transistors 63 of respective such bits, belonging to the same byte, are connected to a common source line 22.
Operation of this EEPROM is now described.
The memory transistor 63 stores a binary signal, depending on whether or not its floating gate stores electrons. If the floating gate stores electrons, the threshold voltage of the memory transistor 63 is increased to turn off the same in read operation. It is assumed that information "1" is stored in this state. When the floating gate stores no electrons, on the other hand, the threshold voltage of the transistor 63 goes negative to turn on the same in read operation. It is assumed that information "0" is stored in this state.
The sense amplifier 56 supplies voltage for reading to the bit line 5 through the transistor 68. This voltage is further supplied to the memory transistor 63 through the transistor 62. Thus, the sense amplifier 56 detects whether or not current flows to the memory transistor 63, thereby to read the signal stored in the memory transistor 63.
FIG. 10 is a sectional view showing the structure around a memory transistor of the conventional EEPROM.
This structure is disclosed in Japanese Patent Laying-Open Gazette No. 80779/1982. Brief description is now made on the structure and the operation thereof, in correspondence to FIG. 9.
N-type impurity regions 8, 9 and 10 are formed with prescribed spaces on an active region defined by an isolation oxide film 6 on the major surface of a semiconductor substrate 1 of P-type silicon. A gate 2 of the select transistor 62 is formed on a region between the impurity regions 8 and 9, through an insulating film 11. A floating gate 3 of the memory transistor 63 is formed in the configuration shown in FIG. 10 in the impurity region 9 through a thin insulating film 14 for serving as a tunnel oxide film. A control gate 4 of the memory transistor 63 is formed on the floating gate 3 in a configuration similar to that of the floating gate 3. The select gate 2, the floating gate 3 and the control gate 4 are entirely covered with an insulating film. The impurity region 8 for serving as a drain region of the select transistor 62 is connected to the bit line 5, while the impurity region 10 for serving as a source region of the memory transistor 63 is connected to the source line 22.
In erase operation of injecting electrons into the floating gate 3, the word line 20 is selected to apply high voltage to the select gate 2, thereby to select the cell. The bit line 5 and the source line 22 are zeroized in voltage while high voltage is applied to the control gate 4, whereby electrons are injected into the floating gate 3 from the drain region 9 through the tunnel oxide film 14.
In write operation of extracting electrons from the floating gate 3, the word line 20 is selected to apply high voltage to the select gate 2, thereby to select the cell. Then the source line 22 is floated and the voltage at the control gate 4 is zeroized to apply high voltage to the bit line 5, whereby the electrons are extracted from the floating gate 3 to the drain region 9 through the tunnel oxide film 14.
Tunneling operation is described in detail in, for example, "On tunneling in metal-oxide silicon structures" by Z. A. Weinberg in J. Appl. Phys. 53(7), pp. 5052-5056, 1982.
In read operation, the word line 20 is selected to apply prescribed voltage to the select gate 2, thereby to select the cell. The voltage at the source line 22 is zeroized and positive voltage is supplied to the bit line 5, thereby to apply bias voltage for reading to the control gate 4. Drain current, which is varied with presence/absence of charge storage in the floating gate 3, is detected thereby to read the stored information "1" or "0".
Table 1 shows voltage levels of the respective parts of the EEPROM in respective operating modes, with application of program voltage of 18 V.
TABLE 1 ______________________________________ Mode Node Write Erase Read ______________________________________ Word Line 18 V 18 V 5 V (Select Gate) Bit Line 18 V 0 V 1 V (Aluminum Wire) Control Gate 0 V 18 V 2 V Source Line Floating State 0 V 0 V ______________________________________
In the aforementioned conventional non-volatile semiconductor memory device, inconvenience is caused in an operating mode for writing.
When electrons are gradually extracted from the floating gate 3 in write operation, the threshold voltage of the memory transistor 63 formed by the drain region 9 and the source region 10 goes negative at a certain point of time, to turn on the same. Thus, the drain region 9 and the source region 10 enter conducting states, while the source line 22, to which the source region 10 is connected, is in a floating state Assuming that the voltage of 18 V is applied to the drain region 9 as hereinabove described, the potential at the source region 10, i.e., that at the source line 22 is increased to 7 to 8 V.
Within the memory cells of the same byte having the source line 22 in common, which is shown in FIG. 9, note a memory cell which is not selected in the write operation. The aforementioned voltage of 7 to 8 V is also applied to the source region of the memory transistor of the non-selected cell through its tunnel oxide film. When such voltage application of 7 to 8 V is only once, electrons in the floating gate of the non-selected memory transistor are not entirely extracted to its source region. However, if such voltage is applied about 10.sup.4 to 10.sup.5 times, a considerable amount of the electrons may be extracted from the floating gate to the source region. Even if the electrons are not entirely extracted, the margin of the storage capacity of the memory cell is reduced by partial extraction of the electrons, to lose allowance for noise. Thus, possibility of causing a read error is increased.
In order to manufacture the EEPROM shown in FIG. 10, further, it has been inevitably required to widen the drain region 9 beyond necessity, to correctly position the tunnel oxide film 14. In other words, the impurity for forming the drain region 9 is injected through a mask of a resist film which is formed by exposure technique, and hence misalignment of such a mask must be taken into consideration. Thus, the conventional manufacturing method is rather disadvantageous for refinement of EEPROM.